PGA_VCM_DIR=DOWN, VREF_GAIN=VREF_GAIN_1X, ADC_GAIN=ADC_GAIN_0P5X, SCAN_INTV=SCAN_INTV_2CLK, PGA_VINN=VREF, ADC_VCM=ADC_VCM_1D16
ADC configuration register
| PGA_GAIN | SD ADC input PGA gain=2^value the range is 1-16. |
| PGA_BP | 1 to bypass SD ADC input PGA |
| PGA_VINN | SD ADC PGA VIN input offset selection 0 (VREF): VREF 1 (VREF_0P75): 3/4 VREF 2 (VREF_0P5): 1/2 VREF 3 (AVSS): AVSS |
| ADC_GAIN | SD ADC gain selection. 0 (ADC_GAIN_0P5X): 0.5x 1 (ADC_GAIN_1X): 1x 2 (ADC_GAIN_1P5X): 1.5x 3 (ADC_GAIN_2X): 2x |
| VREF_GAIN | SD ADC Reference Gain seletion 0 (VREF_GAIN_1X): 1x 1 (VREF_GAIN_1P5X): 1.5x |
| ADC_VCM | SD ADC input common voltage selection. 0 (ADC_VCM_1D16): 1/16 VCC 1 (ADC_VCM_1D8): 1/8 VCC 2 (ADC_VCM_2D8): 2/8 VCC 3 (ADC_VCM_3D8): 3/8 VCC 4 (ADC_VCM_4D8): 4/8 VCC 5 (ADC_VCM_5D8): 5/8 VCC 6 (ADC_VCM_6D8): 6/8 VCC 7 (ADC_VCM_7D8): 7/8 VCC |
| PGA_VCM_EN | SD ADC PGA output common voltage control enable signal. |
| PGA_VCM_DIR | SD ADC PGA output common voltage control direction signal. 0 (DOWN): down 1 (UP): up |
| PGA_VCM | SD ADC PGA output common voltage, adjustment = (PGA_VCM0[5]+1)*(PGA_VCM0[3:0]+1)*40mv |
| DOWN_SAMPLE_RATE | Down sample rate 1 (DOWN_SAMPLE_32): down sample 32 3 (DOWN_SAMPLE_64): down sample 64 4 (DOWN_SAMPLE_256): down sample 256 5 (DOWN_SAMPLE_128): down sample 128 |
| DS_DATA_STABLE | Down sample date stable number. you can keep the bit 1:0 to 2’b11. DS_DATA_STABLE0[5:2]+1 |
| SCAN_INTV | Interval when switching ADC source; 2/4/8/16/32/64/128/256 clock cycle. 0 (SCAN_INTV_2CLK): 2 clock cycle 1 (SCAN_INTV_4CLK): 4 clock cycle 2 (SCAN_INTV_8CLK): 8 clock cycle 3 (SCAN_INTV_16CLK): 16 clock cycle 4 (SCAN_INTV_32CLK): 32 clock cycle 5 (SCAN_INTV_64CLK): 64 clock cycle 6 (SCAN_INTV_128CLK): 128 clock cycle 7 (SCAN_INTV_256CLK): 256 clock cycle |